The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same; and, more particularly, the invention relates to a technique which may be advantageously applied to a system on chip wherein a flash memory (EEPROM: electrically erasable programmable ROM) and a CMOS logic circuit (complementary metal oxide semiconductor logic circuit) are mounted on one chip, or to a system wherein a DRAM (dynamic random access memory) and a CMOS logic circuit are mounted on one chip.
In the field of advanced technologies such as multi-media and data communication, an effort is recently being put into the development of systems on chip wherein a microcomputer, DRAM, ASIC (application specific integrated circuit), flash memory and the like are mounted on one chip for higher data rates, reduced space requirements (improved packaging density) and lower power consumption.
For example, needs for reduced power consumption in the market have accelerated a trend toward lower voltages. Specifically, the power supply voltage has been reduced from 5 V to 3.3 V. This trend toward low power has opened the door to products of 0.25 micron processing in the field of LSI (large scale integrated circuit) processing techniques, and the main stream of such products is systems which operate on 2.5 V or 1.8 V, interface at a high voltage and operate on a low operating voltage internally.
Referring to device structures, the trend toward higher fineness and higher speeds has spotlighted techniques to achieve lower resistance using a refractory metal silicide film. Especially, the use of a technique for reducing resistance referred to as a xe2x80x9csalicide (self-aligned suicide) techniquexe2x80x9d is effective in providing a system on chip.
The following known articles numbered 1 through 7 disclose salicide techniques.
(1) Japanese laid-open patent publication No. H7-211898 (article 1)
Article 1 discloses a semiconductor device for maintaining the durability of a gate oxide film of a semiconductor device at an I/O portion and a method of manufacturing the same. It also discloses a technique applied to a CMOS, characterized in that a diffusion layer having a concentration lower than that in the source and drain diffusion layers is formed between the source and drain diffusion layers and a gate and in that the low concentration diffusion layer is a non-salicide region unlike the source and drain diffusion regions. The known article 1 will be described later in more detail.
(2) Japanese laid-open patent publication No. H7-106559 (article 2)
Article 2 discloses a method of, manufacturing a semiconductor device in which high reliability and cost reduction is achieved by simultaneously forming an insulation film covering the sides of a gate electrode and an insulation film covering the boundary between a device isolating region and a transistor active region. It also discloses a technique for reducing leakage during processing of a side spacer insulation film (silicon oxide film) around a gate by extending a mask up to the end of the device isolating region to leave it, thereby offsetting the source, drain and a suicide film from the device isolating region.
(3) Japanese laid-open patent publication No. H7-183506 (article 3)
Article 3 discloses a transistor having a structure which minimizes both of the layer resistance of a titanium suicide film that constitutes a gate electrode and the layer resistance of a titanium silicide film that constitute source and drain regions having a salicide structure. It also discloses a technique in which a polycrystalline silicon film dominated by (111)-orientation is used as the gate electrode on which the titanium silicide film is formed. That is, the article 1 presents a salicide technique based on the formation of titanium silicide on a gate electrode.
(4) Japanese laid-open patent publication No. H7-263682 (article 4)
Article 4 discloses a method of manufacturing a MISFET having a salicide structure which makes it possible to reduce leakage current and to reduce parasitic resistance.
According to Article 4, a first diffusion layer is formed using ion implantation and a heating process; thereafter, second ion implantation is carried out using side walls as a mask to form a second diffusion layer; and rapid thermal annealing (RTA) is used to activate the impurity in the second diffusion layer. This removes crystal defects in the diffusion layer as a result of the ion implantation and prevents any reduction of the concentration of the impurity in the vicinity of the interface between the surface of the diffusion layer and the bottom of a silicide layer to reduce parasitic resistance.
(5) Japanese laid-open patent publication No. H9-82949 (article 5)
Article 5 discloses a semiconductor device which has less leakage current and an operation speed higher than that in a case wherein neither metal suicide layer nor metal layer is formed on the source and drain regions and a method of manufacturing the same. According to Article 5, an offset layer is formed between the interface of a p-n junction of the source and drain and the end of a metal silicide layer or metal layer in order to suppress the generation of any leakage current between them. The offset layer is controlled by the thickness of a side wall spacer provided on a side wall of the gate (the width of the side wall in the direction of the channel length).
(6) Japanese laid-open patent publication No. H10-12748 (article 6)
Article 6 discloses a CMOS semiconductor device having a structure comprised of different types of gates (dual gate structure) formed by introducing impurities of different conductivity types and discloses the use of a salicide structure and the use of titanium (Ti) or cobalt (Co) as a specific metallic material to provide the salicide structure.
The following articles disclose techniques for providing a plurality of MISFETs with an LDD (lightly doped drain) structure having various electrical characteristics to be incorporated in one semiconductor substrate.
(7) Japanese laid-open patent publication No. S62-283666 (article 7)
Article 7 discloses a technique in which the width of a side wall is changed to change the width of a semiconductor region having a high impurity concentration located under the side wall. That is, there is provided MISFETs having different offset widths of the regions between the ends of the gate electrodes and the ends of the semiconductor regions having a high impurity concentration. Article 7 does not disclose any application of the salicide technique.
(8) Japanese laid-open patent publication No. S63-226055 (article 8)
Article 8 discloses a technique for maintaining the withstand voltage of an n-channel MISFET and for improving the current driving capability of a p-channel MISFET. According to the technique disclosed in article 8, the dimensions of an LDD portion of an n-channel MISFET are increased to separate the source and drain regions having a high impurity concentration and to thereby maintain the withstand voltage between those regions, and the dimensions of an LDD portion of a p-channel MISFET are decreased to reduce series resistance of the source region and series resistance of the drain region and to thereby improve current driving capability. Article 8 does not also disclose any application of the salicide technique.
In a system on chip incorporating a flash memory array and a logic circuit such as a microcomputer, for example, an external power supply of 3.3 V is used which results in a need for a plurality of MISFETs to be driven at the external power supply of 3.3 V, and a first internal power supply voltage of 1.8 V is generated by a voltage reduction circuit for reduced power consumption and increased speed which results in a need for a plurality of MISFETs to be driven at the first internal power supply voltage. Further, a second internal power supply voltage in the range from 10 V to 12 V is generated by a boosting circuit, which results in a need for a plurality of MISFETs to be driven at the second internal power supply voltage (10 to 12 V) for purposes including writing into selected memory cells in the flash memory array. Hereinafter, the former MISFETs driven at the voltage of 3.3 V or 1.8 V are referred to as xe2x80x9clow withstand voltage MISFETsxe2x80x9d, and the latter MISFETs driven at the voltage in the range from 10 to 12V are referred to as xe2x80x9chigh withstand voltage MISFETsxe2x80x9d. Each of the low withstand voltage MISFETs and high withstand voltage MISFETs is incorporated in one semiconductor body (semiconductor chip) in the form of a CMOS (a pair of a p-channel MISFET and an n-channel MISFET).
A possible solution to improve the capability of the devices (MISFETs) forming the system on chip is to reduce the resistance of the gate electrode and the diffusion layers (source and drain regions) using the salicide technique.
Further, a device-related technique for a second internal power supply circuit (high voltage power supply circuit) in a system on chip has been conceived in which a diffusion layer having a high concentration (contact region) is offset from a gate electrode and a field oxide film. Such a device is referred to as xe2x80x9coffset MOSxe2x80x9d.
This technique makes it possible to increase the withstand voltage of a diffusion layer, thereby maintaining a margin to deal with the generation of a high voltage. Specifically, a region having a concentration lower than that of the diffusion layer is provided between a channel region under a gate electrode and the diffusion layer having a higher concentration to offset the channel region and the diffusion layer of a higher concentration. As a result, a high resistance layer constituted only by a region having a low concentration (extension layer) is formed between them, which improves characteristics such as drain-source breakdown voltage (gate voltage open) BVds0 of the device.
In order to manufacture a product in which a flash memory and a microcomputer are mounted on the same chip (i.e., a system LSI) with high device performance, a technique is required which provides the advantages of both of an offset MOS and salicide technique as described above. However, efforts to provide the advantages of the two techniques have revealed the following problems.
Silicidization of a diffusion layer formed with an offset MOS has also silicidized a low concentration diffusion layer (extension layer) in the offset region. This results in an increase of junction leakage attributable to absorption of the impurity in the diffusion layer during the silicidizing reaction.
Further, the offset MOS cannot provide expected performance because of factors including concentration of a current attributable to a reduction in the resistance on the surface thereof. Specifically, the diffusion layer includes a region where the silicide layer (low resistance layer) abruptly changes to the salicide layer (high resistance layer), and a concentration of a current in such a region results in local fusing which in turn deteriorates device characteristics.
One possible solution to this problem is to cover the diffusion layer having a low concentration of the offset MOS with a photoresist mask to form the silicide layer only on the diffusion layer having a high concentration.
The above-described method makes it possible to prevent silicidization on the surface of the low concentration diffusion layer, thereby providing a salicide and an offset MOS in the same chip without deteriorating characteristics.
Referring to the above-mentioned known article 1, FIG. 1(e) shows a semiconductor device at an I/O portion having an offset structure including a non-salicide region. Specifically, a suicide layer (salicide region: TiSi2 13) is selectively formed only on a diffusion layer having a high concentration. As apparent from the above description, such a semiconductor device structure makes it possible to maintain the durability of not only a gate insulation film but also an end of a LOCOS oxide film even when a voltage higher than an operating voltage is applied to the source and drain diffusion layers.
However, this method inevitably results in a cost increase attributable to an increase in the number of masks because it involves a step of covering the surface of a low concentration diffusion layer as described above to prevent it from being silicidized.
A problem also arises in that it is difficult to achieve fineness because layout designing must be carried out in consideration to misalignment between the mask to form a non-silicide region and a diffusion layer surrounding the region.
How to reduce the number of masks is an important technical challenge in achieving a high level of integration of a system on chip at a reduced cost.
This is because a reduction of the number of masks makes it possible not only to reduce the manufacturing cost of masks but also to reduce a series of processes for forming photoresist patterns using the masks, i.e., application, exposure, development, cleaning and drying of the photoresist, which significantly reduces the processing cost of a semiconductor integrated circuit device. Further, it is possible to reduce the rate of occurrence of defects attributable to foreign substances, which makes it possible to improve the yield and reliability of semiconductor integrated circuit devices.
Under such circumstances, the inventors studied the possibility of deletion of the photoresist masking step to form a salicide region of an offset MOS and the study focused on a mask for forming an n+ (high concentration) diffusion layer and a mask for forming a p+ (low concentration) diffusion layer.
It is a first object of the invention to provide a novel semiconductor integrated circuit device incorporating a MISFET capable of operating at a high speed and a MISFET which can be driven at a high voltage.
It is a second object of the invention to provide a method of manufacturing a semiconductor integrated circuit device incorporating MISFETs with channels of the same conductivity type having different characteristics at a low cost and improved production yield.
It is a third object of the invention to provide a novel semiconductor integrated circuit device incorporating a low withstand voltage MISFET and a high withstand voltage MISFET.
It is a fourth object of the invention to provide a method of manufacturing a semiconductor integrated circuit device incorporating a low withstand voltage MISFET and a high withstand voltage MISFET at a low cost.
It is a fifth object of the invention to provide a novel CMOS semiconductor integrated circuit device incorporating a MISFET capable of operating at a high speed and a MISFET which can be driven at a high voltage.
It is a sixth object of the invention to provide a method of manufacturing a CMOS semiconductor integrated circuit device incorporating p-channel MISFETs having different characteristics and n-channel MISFETs having different characteristics at a low cost. It is a seventh object of the invention to provide a novel semiconductor integrated circuit device in which a flash memory and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip.
It is an eighth object of the invention to provide a method of manufacturing a semiconductor integrated circuit device in which a flash memory and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip at a low cost.
It is a ninth object of the invention to provide a novel semiconductor integrated circuit device in which an SRAM and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip.
It is a tenth object of the invention to provide a method of manufacturing a semiconductor integrated circuit device in which an SRAM and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip at a low cost.
It is an eleventh object of the invention to provide a novel semiconductor integrated circuit device in which a DRAM and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip.
It is a twelfth object of the invention to provide a method of manufacturing a semiconductor integrated circuit device in which a DRAM and a logic circuit capable of operating at a high speed are incorporated in a single semiconductor chip at a low cost.
(1) According to a first aspect of the invention, on a semiconductor body having a first semiconductor principal surface and a second semiconductor principal surface separated from each other, there is provided:
a first MISFET formed by
a first gate electrode provided on the first semiconductor principal surface with a gate insulation film interposed therebetween,
a first region having a relatively low concentration which is aligned with the first gate electrode and which exhibits the conductivity type opposite to the conductivity type of the first semiconductor principal surface,
a first insulation film provided on a side wall of the first gate electrode on the first region,
a second region having a relatively high concentration which is aligned with an end of the first insulation film, which exhibits the same conductivity type as the first region and which is in contact with the first region, and
a metal-semiconductor reaction layer on the principal surface in the second region which is aligned with an end of the first insulation film; and a second MISFET formed by
a second gate electrode provided on the second semiconductor principal surface with a gate insulation film interposed therebetween,
a third region having a relatively low concentration which is aligned with the second gate electrode and which exhibits the conductivity type opposite to the conductivity type of the second semiconductor principal surface,
a second insulation film provided on a side wall of the second gate electrode on the third region which is greater than the first insulation film in the width in the direction of the gate length,
a fourth region having a relatively high concentration which is aligned with an end of the second insulation film, which exhibits the same conductivity type as the third region and which is in contact with the third region, and
a metal-semiconductor reaction layer on the principal surface in the fourth region which is aligned with an end of the second insulation film.
According to the above-described first aspect, each of the second region of the first MISFET and the metal-semiconductor reaction layer is aligned with an end of the first insulation film; each of the fourth region of the second MISFET and the metal-semiconductor reaction layer is aligned with an end of the second insulation film; and the resistance of electrode extracting portions of the second and fourth regions is decreased by the metal-semiconductor reaction layers.
Thus, each of the first and second MISFETs can operate at a high speed. Since the second insulation film is wider than the first insulation film, the distance between an end of a p-n junction formed by the second semiconductor and the first region and the metal-semiconductor reaction layer is greater than the distance between an end of a p-n junction formed by the first semiconductor and the second region and the metal-semiconductor reaction layer. This makes it possible to allow a depletion layer to spread in the third region sufficiently, which allows the second MISFET to be provided with a withstand voltage higher than that of the first MISFET, i.e., which makes it possible to provide a MISFET that can be driven at a high voltage.
(2) According to a second aspect of the invention, there is provided:
a first semiconductor and a second semiconductor separated from each other by an insulating isolation layer;
a first MISFET formed by
a first gate electrode provided on the first semiconductor with a gate insulation film interposed therebetween,
a first region having a first impurity concentration which is aligned with the first gate electrode and the insulating isolation layer and which exhibits the conductivity type opposite to the conductivity type of the first semiconductor,
a first insulation film selectively left on a side wall of the first gate electrode on the first region,
a second region which is aligned with the first insulation film and the insulating isolation layer, which is of the same conductivity type as the first region, which exhibits a concentration higher than the first impurity concentration and which is in contact with the first region, and
a metal-semiconductor reaction layer on a principal surface in the second region which is aligned with the first insulation film; and a second MISFET formed by
a second gate electrode provided on the second semiconductor with a gate insulation film interposed therebetween,
a third region having a third impurity concentration which is aligned with the second gate electrode and the insulating isolation layer and which exhibits the conductivity type opposite to the conductivity type of the second semiconductor,
a second insulation film selectively formed on the third region such that it protrudes from a side wall of the second gate electrode and the insulating isolation layer,
a fourth region which is aligned with the second insulation film and the insulating isolation layer, which is of the same conductivity type as the third region, which exhibits a concentration higher than the third impurity concentration and which is in contact with the third region, and
a metal-semiconductor reaction layer on a principal surface in the fourth region which is aligned with the second insulation film. The pattern width of the second gate insulation from an end of the second gate electrode is greater than the pattern width of the first insulation film from an end of the first gate electrode.
According to the above-described second aspect, it is possible to allow a depletion layer to spread in the third region sufficiently, which allows the second MISFET to be provided with a withstand voltage higher than that of the first MISFET. Further, the problem of junction leakage can be solved because the metal-semiconductor reaction layer of the second MISFET is formed apart from the third region and the insulating isolation layer.
(3) According to a third aspect of the invention, there is provided the steps of:
forming a pattern of each of a first gate electrode on a principal surface of a first semiconductor with a first gate insulation film interposed therebetween and forming a second gate electrode on a principal surface of a second semiconductor with a second gate insulation film interposed therebetween;
introducing an impurity exhibiting the conductivity type opposite to the conductivity type of the first semiconductor to a region of the first semiconductor principal surface unmasked by the first gate electrode to form a first region having a first impurity concentration;
introducing an impurity exhibiting the second conductivity type opposite to the first conductivity type of the first semiconductor to a region of the second semiconductor principal surface unmasked by the second gate electrode to form a third region having a third impurity concentration;
forming an insulation film on each of the first semiconductor principal surface having the first gate electrode formed thereon and the second semiconductor principal surface having the second gate electrode formed thereon;
performing anisotropic etching on the insulation film on the first semiconductor principal surface to leave a first insulation film on a side wall of the first gate electrode;
providing a pattern mask on the insulation film on the second semiconductor principal surface and performing pattern etching of the insulation film with the mask to leave a second insulation film on a side wall of the second gate electrode;
introducing an impurity exhibiting the second conductivity type to a region of the first semiconductor principal surface unmasked by the first insulation film to form a second region having a second impurity concentration higher than the first impurity concentration and introducing an impurity exhibiting the second conductivity type to a region of the second semiconductor principal surface unmasked by the second insulation film to form a fourth region having a fourth impurity concentration higher than the third impurity concentration; and
forming a metal-semiconductor reaction layer aligned with the first insulation film and a metal-semiconductor reaction layer aligned with the second insulation film on the surfaces of the second and fourth regions, respectively.
According to the third aspect, since self-aligning formation occurs between the second region and the metal-semiconductor reaction layer on the surface thereof and between the fourth region and the metal-semiconductor reaction layer on the surface thereof as a result of the intervention of the first and second insulation films respectively, the number of masks can be reduced. This makes it possible not only to reduce the manufacturing cost of masks themselves but also to reduce a series of processes for forming photoresist patterns using the masks, i.e., application, exposure, development, cleaning and drying of the photoresist, which significantly reduces the processing cost of a semiconductor integrated circuit device. Further, it is possible to reduce the rate of occurrence of defects attributable to foreign substances, which makes it possible to improve the yield and reliability of semiconductor integrated circuit devices.
(4) According to a fourth aspect of the invention, on a substrate having a first semiconductor region and a second semiconductor region, there is provided:
a first MISFET formed by
a first gate electrode provided on a principal surface of the first semiconductor region with a gate insulation film having a first thickness interposed therebetween,
a first region having a first impurity concentration which is aligned with the first gate electrode, which is provided in the first semiconductor region and which exhibits the conductivity type opposite to the conductivity type of the first semiconductor region,
a first insulation film having a first side wall width selectively formed on a side wall of the first gate electrode on the first region,
a second region which is aligned with the first insulation film, which is of the same conductivity type as the first region, which exhibits a concentration higher than the first impurity concentration and which partially overlaps the first region, and
a metal-semiconductor reaction layer formed on a principal surface of the second region; and
a second MISFET formed by
a second gate electrode provided on the principal surface of the second semiconductor region with a gate insulation film having a second thickness larger than the first thickness interposed therebetween,
a third region having a third impurity concentration which is aligned with the second gate electrode and which is provided in the second semiconductor region and which exhibits the conductivity type opposite to the conductivity type of the first semiconductor region,
a second insulation film having a second side wall width selectively formed on a side wall of the second gate electrode on the third region,
a fourth region which is aligned with the second insulation film, which is of the same conductivity type as the third region, which exhibits a concentration higher than the third impurity concentration and which partially overlaps the third region, and
a metal-semiconductor reaction layer formed on a principal surface of the fourth region.
According to the above-described fourth aspect, higher speed and lower power consumption can be achieved because a metal-semiconductor reaction layer is formed on the surface of each of the second region serving as the contact region of the first MISFET and the fourth region serving as the contact region of the second MISFET to reduce the resistance thereof. Since the fourth region of the second MISFET is formed in alignment with the second insulation film having the second side wall width, an offset length of the third region under the second insulation film is greater than an offset length of the second region under the first insulation film. Therefore, a depletion layer can spread sufficiently in the third region, which makes it possible to provide the second MISFET with a withstand voltage higher than that of the first MISFET.
The term xe2x80x9coffset lengthxe2x80x9d represents the distance between an end of a gate electrode in the direction of the channel length and an end of a high concentration region.
(5) According to a fifth aspect of the invention, there is provided the steps of:
forming a pattern of each of a first gate electrode on a principal surface of a first semiconductor with a first gate insulation film interposed therebetween and forming a second gate electrode on a principal surface of a second semiconductor with a second gate insulation film interposed therebetween;
introducing an impurity exhibiting the conductivity type opposite to the conductivity type of the first semiconductor to a region of the first semiconductor principal surface unmasked by the first gate electrode to form a first region having a first impurity concentration aligned with the first gate insulation film;
introducing an impurity exhibiting the second conductivity type opposite to the first conductivity type of the first semiconductor to a region of the second semiconductor principal surface unmasked by the second gate electrode to form a third region having a third impurity concentration aligned with the second gate electrode;
forming an insulation film on each of the first semiconductor principal surface having the first gate electrode formed thereon and the second semiconductor principal surface having the second gate electrode formed thereon;
performing anisotropic etching on the insulation film on the first semiconductor principal surface to leave a first insulation film on a side wall of the first gate electrode;
providing a pattern mask on the insulation film on the second semiconductor principal surface and performing pattern etching of the insulation film with the mask to leave a second insulation film having a side wall width greater than a side wall width of the first insulation film on a side wall of the second gate electrode;
introducing an impurity exhibiting the second conductivity type to a region of the first semiconductor principal surface unmasked by the first insulation film to form a second region having a second impurity concentration higher than the first impurity concentration aligned with the first insulation film and introducing an impurity exhibiting the second conductivity type to a region of the second semiconductor principal surface unmasked by the second insulation film to form a fourth region having a fourth impurity concentration higher than the third impurity concentration aligned with the second insulation film; and
forming a metal-semiconductor reaction layer aligned with the first insulation film and a metal-semiconductor reaction layer aligned with the second insulation film on the surfaces of the second and fourth regions, respectively.
According to the fifth aspect, the width of the second region from an end of the second gate electrode to an end of the fourth region can be greater than the width of the first region from an end of the first gate electrode to an end of the second region. As a result, the first MISFET has the device performance (characteristics) of a low withstand voltage MISFET in that it operates at a high speed and it is suitable for driving at a relatively low voltage. Meanwhile, the second MISFET has the device performance (characteristics) of a high withstand voltage MISFET in that it operates at a low speed and it is suitable for driving at a relatively high voltage. Further, since self-aligning formation occurs between the second region and the metal-semiconductor reaction layer on the surface thereof and between the fourth region and the metal-semiconductor reaction layer on the surface thereof as a result of the intervention of the first and second insulation films respectively, the number of masks can be reduced. This makes it possible to reduce the processing cost of a semiconductor integrated circuit device significantly.
(6) According to a sixth aspect of the present invention, there is provided a CMIS semiconductor integrated circuit device comprising:
a first well of a first conductivity type and a second well of a second conductivity type opposite to the first conductivity type which are separated from each other on a single semiconductor body;
a first MISFET having a channel of the second conductivity type formed by
a first gate electrode provided on a principal surface of the first well with an insulation film interposed therebetween,
a first region of the second conductivity type formed in the first well,
a first insulation film provided on a side wall of the first gate electrode on the first region,
a second region of the second conductivity type which is aligned with the first insulation film and which is in contact with the first region, and a metal-semiconductor reaction layer aligned with the first insulation film on a principal surface of the second region; and
a second MISFET having a channel of the first conductivity type formed by
a second gate electrode provided on a principal surface of the second well with an insulation film interposed therebetween,
a third region of the first conductivity type formed in the second well,
a second insulation film provided on a side wall of the second gate electrode on the third region,
a fourth region of the first conductivity type which is aligned with the second insulation film and which is in contact with the third region, and
a metal-semiconductor reaction layer aligned with the second insulation film on a principal surface of the fourth region.
According to the sixth aspect, the second region serving as a contact region for the first MISFET (specifically a p-channel MISFET) and the metal-semiconductor reaction layer formed on the surface of the second region are aligned with the first insulation film, and the fourth region serving as a contact region for the second MISFET (specifically an n-channel MISFET) and the metal-semiconductor reaction layer formed on the surface of the fourth region are aligned with the second insulation film. The presence of the metal-semiconductor layers reduces the resistance of the second and fourth regions. The means employed in the present invention for solving typical problems that it confronts and operations of the same have been briefly described above. The solving means according to the invention for achieving the above-described objects will become apparent from preferred embodiments of the invention described below.